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E2G0031-17-41
Semiconductor MSM519205
Semiconductor
This version: Jan. 1998 MSM519205 Previous version: May 1997
4,194,304-Word 2-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM519205 is a 4,194,304-word 2-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM519205 achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM519205 is available in a 26/24-pin plastic SOJ or 26/24-pin plastic TSOP.
FEATURES
* 4,194,304-word 2-bit configuration * Single 5 V power supply, 10% tolerance * Input : TTL compatible, low input capacitance * Output : TTL compatible, 3-state * Refresh : 2048 cycles/32 ms * Fast page mode with EDO, read modify write capability * CAS before RAS refresh, hidden refresh, RAS-only refresh capability * Multi-bit test mode capability * Package options: 26/24-pin 300 mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM519205-xxSJ) 26/24-pin 300 mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM519205-xxTS-K) xx indicates speed rank.
PRODUCT FAMILY
Family MSM519205-60 MSM519205-70 MSM519205-80 Access Time (Max.) tRAC tAA tCAC tOEA 60 ns 30 ns 15 ns 15 ns 70 ns 35 ns 20 ns 20 ns 80 ns 40 ns 20 ns 20 ns Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 110 ns 130 ns 150 ns 440 mW 413 mW 385 mW 5.5 mW
1/18
Semiconductor
PIN CONFIGURATION (TOP VIEW)
VCC 1
26 VSS 25 NC VCC 1 DQ1 2 WE 4 NC 6 DQ1 2 WE 4 NC 6 DQ2 3 24 CAS1 23 CAS2 22 OE 21 A9 19 A8 DQ2 3 RAS 5 RAS 5 A10 8 A0 9 A10 8 18 A7 17 A6 16 A5 15 A4 14 VSS A0 9 A1 10 A2 11 A3 12 VCC 13 A1 10 A2 11 A3 12 VCC 13 26/24-Pin Plastic SOJ Pin Name A0 - A10 RAS CAS1, CAS2 DQ1, DQ2 OE WE VCC VSS NC Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5 V) Ground (0 V) No Connection
MSM519205
26 VSS 25 NC 24 CAS1 23 CAS2 22 OE 21 A9 19 A8 18 A7 17 A6 16 A5 15 A4 14 VSS
26/24-Pin Plastic TSOP (K Type)
Note :
The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.
2/18
Semiconductor
MSM519205
BLOCK DIAGRAM
Timing Generator Timing Generator
RAS CAS1 CAS2
11
Column Address Buffers Internal Address Counter
11
Column Decoders
Write Clock Generator
WE OE
2
Output Buffers
2 2
A0 - A10
Refresh Control Clock
Sense Amplifiers
2
I/O Selector
2 2
DQ1, DQ2
Input Buffers
2
11
Row Address Buffers
11
Row Decoders
Word Drivers
Memory Cells
VCC On Chip VBB Generator VSS
FUNCTION TABLE
Input Pin RAS H L L L L L L L L CAS1 * H L H L L H L L CAS2 * H H L L H L L L WE * * H H H L L L H OE * * L L L H H H H DQ1 High-Z High-Z DOUT High-Z DOUT DIN Don't Care DIN High-Z DQ Pin DQ2 High-Z High-Z High-Z DOUT DOUT Don't Care DIN DIN High-Z Function Mode Standby Refresh DQ1 Read DQ2 Read DQ1, DQ2 Read DQ1 Write DQ2 Write DQ1, DQ2 Write --
*: "H" or "L"
3/18
Semiconductor
MSM519205
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating -1.0 to 7.0 50 1 0 to 70 -55 to 150 Unit V mA W C C
*: Ta = 25C Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -1.0 Typ. 5.0 0 -- -- Max. 5.5 0 6.5 0.8 (Ta = 0C to 70C) Unit V V V V
Capacitance
Parameter Input Capacitance (A0 - A10) Input Capacitance (RAS, CAS1, CAS2, WE, OE) Output Capacitance (DQ1, DQ2) Symbol CIN1 CIN2 CI/O Typ. -- -- --
(VCC = 5 V 10%, Ta = 25C, f = 1 MHz) Max. 6 7 10 Unit pF pF pF
4/18
Semiconductor DC Characteristics
Parameter Output High Voltage Output Low Voltage Input Leakage Current Condition
MSM519205
(VCC = 5 V 10%, Ta = 0C to 70C)
Symbol
MSM519205 MSM519205 MSM519205 -60 -70 -80 Unit Note Min. Max. VCC 0.4 10 Min. 2.4 0 -10 Max. VCC 0.4 10 Min. 2.4 0 -10 Max. VCC 0.4 10 V V mA 2.4 0 -10
VOH IOH = -5.0 mA VOL IOL = 4.2 mA 0 V VI 6.5 V; ILI All other pins not under test = 0 V DQ disable 0 V VO 5.5 V RAS, CAS1, CAS2 ICC1 cycling, tRC = Min. RAS, CAS1, CAS2 = VIH ICC2 RAS, CAS1, CAS2 VCC -0.2 V RAS cycling, ICC3 CAS1, CAS2 = VIH, tRC = Min. RAS = VIH, ICC5 CAS1, CAS2 = VIL, DQ = enable RAS cycling, ICC6 CAS1, CAS2 before RAS RAS = VIL, ICC7 CAS1, CAS2 cycling, tHPC = Min.
Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode)
ILO
-10
10
-10
10
-10
10
mA
-- -- --
80 2 1
-- -- --
75 2 1
-- -- --
70 2 1
mA 1, 2
mA
1
--
80
--
75
--
70
mA 1, 2
--
5
--
5
--
5
mA
1
--
80
--
75
--
70
mA 1, 2
--
100
--
95
--
80
mA 1, 3
Notes : 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS1, CAS2 = VIH.
5/18
Semiconductor AC Characteristics (1/2)
MSM519205
(VCC = 5 V 10%, Ta = 0C to 70C) Note 1, 2, 3, 12, 13 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS Data Output Hold After CAS Low CAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode with EDO) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode with EDO) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge OE Hold Time from CAS (DQ Disable) RAS to CAS Delay Time RAS to Column Address Delay Time RAS to Second CAS Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time
Symbol
MSM519205 MSM519205 MSM519205 -70 -80 -60 Unit Note Min. Max. -- -- -- -- 60 15 30 35 15 -- -- 15 15 15 15 50 32 -- 10,000
100,000
Min. 130 185 30 100 -- -- -- -- -- 0 5 0 0 0 0 2 -- 50 70 70 20 10 10 10 45 10 40 10 20 15 70 0 10 0 15 45 35
Max. -- -- -- -- 70 20 35 40 20 -- -- 15 15 15 15 50 32 -- 10,000
100,000
Min. 150 205 35 105 -- -- -- -- -- 0 5 0 0 0 0 2 -- 60 80 80 20 10 10 15 50 10 45 10 20 15 80 0 10 0 15 50 40
Max. -- -- -- -- 80 20 40 45 20 -- -- 15 15 15 15 50 32 -- 10,000
100,000
tRC tRWC tHPC tHPRWC tRAC tCAC tAA tCPA tOEA tCLZ tDOH tCEZ tOEZ tWEZ tT tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tCHO tRCD tRAD tRSCD tASR tRAH tASC tCAH tAR tRAL
110 155 25 85 -- -- -- -- -- 0 5 0 0 0 0 2 -- 40 60 60 15 10 10 10 40 10 35 5 20 15 60 0 10 0 10 40 30
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 14 14 5 6 15 17 7, 8 7, 8 7 7 3 4, 5, 6 4, 5 4, 6 4, 15 4 4
RAS to Data Output Buffer Turn-off Delay Time tREZ
-- -- -- 10,000 -- -- -- -- 45 30 -- -- -- -- -- -- --
-- -- -- 10,000 -- -- -- -- 50 35 -- -- -- -- -- -- --
-- -- -- 10,000 -- -- -- -- 60 40 -- -- -- -- -- -- --
6/18
Semiconductor AC Characteristics (2/2)
MSM519205
(VCC = 5 V 10%, Ta = 0C to 70C) Note 1, 2, 3, 12, 13 Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width WE Pulse Width (DQ Disable) OE Command Hold Time OE Precharge Time OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) MSM519205 MSM519205 MSM519205 -60 -70 -80 Unit Note Symbol Min. tRCS tRCH tRRH tWCS tWCH tWCR tWP tWPE tOEH tOEP tOCH tRWL tCWL tDS tDH tDHR tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tWRP tWRH tWTS tWTH 0 0 0 0 10 45 10 5 15 10 10 15 15 0 15 40 15 40 55 85 60 10 10 20 10 10 10 20 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 0 0 0 0 15 50 10 10 20 10 10 20 20 0 15 45 20 50 65 100 70 10 10 20 10 10 10 20 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 0 0 0 0 15 55 10 10 20 10 10 20 20 0 15 50 20 50 70 110 75 10 10 20 10 10 10 20 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 10 10, 15 14 14 15 16 11, 14 11, 14 14 9, 14 9 10, 14 14
7/18
Semiconductor Notes:
MSM519205
1. A start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.) , tRWD tRWD (Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. In a test mode CA0, CA1 and CA10 are not used and each DQ pin now accesses 8-bit locations. Since all 2 DQ pins are used, a total of 16 data bits can be written in parallel into the memory array. In a read cycle, if 8 data bits are equal, the DQ pin will indicate a high level. If the 8 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RASonly refresh cycle or a CAS before RAS refresh cycle. 13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 14. These parameters are determined by the falling edge of either CAS1 or CAS2, whichever is earlier. 15. These parameters are determined by the rising edge of either CAS1 or CAS2, whichever is later. 16. tCWL should be satisfied by both CAS1 and CAS2. 17. tCP is determined by the time both CAS1 and CAS2 are high.
8/18
Semiconductor Notes concerning CAS1 and CAS2 control
MSM519205
Overlap the active-low timings of CAS1 and CAS2. Skew between CAS1 and CAS2 is allowed under the following conditions: (1) The timing specification for CAS1 and CAS2 should be met individually. (2) Different operation modes for CAS1/CAS2 are not allowed (as shown below).
RAS
CAS1
Delayed write
CAS2
Early write
WE
(3) Closely separated CAS1/CAS2 control is not allowed. However, when the condition (tCP tUL) is satisfied, fast page mode can be performed.
RAS
CAS1
CAS2 tUL
9/18
E2G0099-17-41L Semiconductor MSM519205
,,, , ,, , ,,,,
TIMING WAVEFORM
Read Cycle
tRC tRAS tRP RAS VIH - VIL - tAR tCRP tCSH tCRP tRCD VIH - CAS VIL - VIH - VIL - VIH - VIL - VIH - VIL - VOH - tRAD tRSH tCAS tRAL tASR tRAH tASC tCAH Address Row Column tRCS tRRH tRCH WE tAA tROH tOEA tREZ OE tRAC tCAC tOEZ tCEZ DQ VOL - Open Valid Data-out tCLZ "H" or "L"
Write Cycle (Early Write)
tRC
tRAS
tRP
RAS
VIH - VIL -
tAR
tCRP
tCRP
tCSH
tRCD
tRSH
VIH - CAS VIL - VIH - VIL - VIH - VIL -
tRAD tRAH
tCAS
tASR
tASC
tCAH
tRAL
Address
Row
Column
tWCS
WE
tWCH tWP
tCWL
tWCR
tRWL
VIH - OE VIL - VIH -
tDS
tDHR
tDH
DQ
VIL -
Valid Data-in
Open
"H" or "L"
10/18
,,,
Semiconductor MSM519205 Read Modify Write Cycle
tRWC tRAS tRP VIH - RAS VIL - tAR tCSH tCRP tCRP tRCD tRSH CAS VIH - VIL - tCAS tASR tRAH tASC tCAH VIH - Address VIL - WE OE VIH - VIL - VIH - VIL - VI/OH- Row Column tRAD tRWD tCWD tAA tAWD tCWL tRWL tWP tRCS tOEA tOED tOEH tCAC tRAC tOEZ tDS tDH DQ VI/OL- tCLZ Valid Data-out Valid Data-in "H" or "L"
11/18
Semiconductor
Fast Page Mode Read Cycle (Part-1)
Address
Fast Page Mode Read Cycle (Part-2)
Address
, ,,, , ,
MSM519205
tRASP tRP RAS VIH - VIL - tRSCD tAR tRHCP tCRP tRCD tHPC tCP tCP CAS VIH - VIL - tCAS tCAS tCAS tRAD tASR tRAH tASC tCSH tCAH tASC tCAH tASC tCAH VIH - VIL - VIH - VIL - VIH - VIL - Row Column Column Column tRCS tRRH WE tCHO tOCH tRAC tAA tOEP OE tAA tAA tOEP tOEA tCAC tCPA tDOH tCAC tOEA tOEA tOEZ tCAC tOEZ tREZ DQ VOH - VOL - tCLZ
Valid Data-out
Valid Data-out Valid* Data-out Valid* Data-out
* : Same Data,
"H" or "L"
tRASP
tRP
RAS
VIH - VIL -
tRSCD
tAR
tRHCP
tCRP
tCRP
tHPC
tRCD
tCP
tCP
CAS
VIH - VIL -
tCAS
tCAS
tCAS
tRAD
tASR
tRAH
tCSH tASC tCAH Column
tASC
tCAH
tASC
tCAH
VIH - VIL - VIH - VIL - VIH - VIL -
Row
Column
Column
tRCS
tRCS
WE
tRAC tAA
tRCH
tWPE
tAA
tAA
OE
tCPA
tOEA tCAC
tWEZ
tCAC
tCAC tDOH
tCEZ
DQ
VOH - VOL -
tCLZ
Valid Data-out
Valid Data-out
Valid Data-out
"H" or "L"
12/18
,, , , ,
Semiconductor MSM519205 Fast Page Mode Write Cycle (Early Write)
tRSCD VIH - VIL - tRASP tRP RAS tAR tCRP tRCD tHPC tHPC tCP tCP CAS VIH - VIL - tCAS tCAS tCAS tRAD tASR tRAH tCSH tASC tCAH Column tASC tCAH tASC tRSH tCAH Address VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL - Row Column Column tWCS tWCH tWCS tWCH tWCS tWCH WE OE tDHR tDS tDH tDS tDH tDS tDH DQ Valid Data-in Valid Data-in Valid Data-in "H" or "L"
Fast Page Mode Read Modify Write Cycle
tRSCD
tRASP
RAS
VIH - VIL -
tRWD
tAR
tCRP
tRCD
tCP
CAS
VIH - VIL -
tRAD
tCWD
tASR
tRAH tASC
tHPRWC
tCPWD tASC
tCAH
tCWL
tCPA tCAH
tRWL
Address
VIH - VIL -
Row
Column
Column
tRCS
tAWD
tRCS
tCWD
WE
VIH - VIL -
tRAC
tAWD
tAA
tDS tWP
tAA
tDS
tWP
OE
VIH - VIL -
tOEA
tOED
tOEH tDH
tOEA
tOED
tOEH tDH
tCAC
tOEZ
tCAC
tOEZ
DQ
VI/OH - VI/OL -
Valid Data-out
Valid Data-in
Valid Data-out
Valid Data-in
tCLZ
tCLZ
"H" or "L"
13/18
Semiconductor RAS-Only Refresh Cycle
t RC tRAS RAS V IH - V IL - tCRP CAS V IH - V IL - tASR Address V IH - V IL - tCEZ DQ V OH - V OL - Open Note: WE, OE = "H" or "L" Row tRAH tRPC tRP
MSM519205
"H" or "L"
CAS before RAS Refresh Cycle
tRC t RP RAS VIH - VIL - tRPC tCP CAS VIH - VIL - tWRP WE VIH - VIL - t CEZ DQ VOH - VOL - Open Note: OE, Address = "H" or "L" "H" or "L" tWRH tWRP tCSR tCHR tRAS t RPC tRP
14/18
Semiconductor
Hidden Refresh Read Cycle
,,, ,, ,, ,
MSM519205
tRC tRAS tRP tRC tRAS tRP RAS VIH - VIL - tAR tCRP tRCD tRSH tCHR CAS VIH - VIL - VIH - VIL - VIH - VIL - tASR tRAH tRAD tASC tCAH Address Row Column tRCS tRAL tRRH WE tAA tROH OE VIH - VIL - tOEA tRAC tCAC tCLZ tCEZ tOEZ tREZ DQ VOH - VOL - Open Valid Data-out "H" or "L"
Hidden Refresh Write Cycle
tRC tRAS
tRP
tRC tRAS
tRP
RAS
VIH - VIL - VIH - VIL -
tAR
tCRP
tRCD
tRSH
tCHR
CAS
tASR
tRAH
tRAD tASC
tCAH
tRAL
Address
VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL -
Row
Column
tWCS
tRWL tWCH
WE
tWP
tWCR
OE
tDS
tDH
DQ
Valid Data-in tDHR "H" or "L"
15/18
Semiconductor
Test Mode Initiate Cycle
RAS
CAS
WE
DQ
,
MSM519205
tRC tRP tRAS VIH - VIL - tRPC tCP tCSR tCHR VIH - VIL - tWTS tWTH VIH - VIL - tOFF VOH - VOL - Open Note: OE, Address = "H" or "L" "H" or "L"
16/18
Semiconductor
MSM519205
PACKAGE DIMENSIONS
(Unit : mm)
SOJ26/24-P-300-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
17/18
Semiconductor
MSM519205
(Unit : mm)
TSOPII26/24-P-300-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.29 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
18/18

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